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SpaceWire based chipset “MultiBoard” for space applications

The "MultiBoard" chipset has been designed and fabricated using ELVEES radiation proofing methodology and Rad Hard library for 0,25–0,09 micron CMOS process technology.

Radiation Tolerant for mass production chips (engineering samples) apply least 100–200 Krad on Total Dose and resistance to Single Event Upset (SEU) under heavy ion streams (preliminarily, confirmed by test chips measurements. Prototype chips have been tested successfully at radiation levels of about 200-krads and had sustained no radiation-induced latch-ups and few soft error events per bit per day. Some chips will be tested on the Russian satellite technology board and available as radiation-tolerant components for all space missions in earth-orbiting satellites applications in 2014.

"MultiBoard" chipset extension can be develop with any cooperation. ASICs can be done as Digital or Mixed Signal complex "System on Chip" for a 6–18 months depending on its complexity. ASIC project can start from the architectural level up to chip development, validation and verification at the Customer's request.

Tools and Software for the SpaceWire based chipsets will be done also. Space quality level: tests and measurements can be performed on the customer's request in Russia, in Europe or anywhere.


ASIC

Technical characteristics (preliminarily)


MCT-03P — Radiation Tolerant microprocessor

MCT-03P — Radiation Tolerant microprocessor/
Mass-storage controller with GigaSpaceWire link

  • CMOS, 0.18 mcm; Radiation Tolerant (RHBD Lib); ASIC design complexities up to 19,200,000 usable transistors;

  • Core Supply Voltage -1,8 V ±5%; I/O Supply Voltage -3,3 V ±5%;

  • Architecture: MIPS32 compatible RISC core & FPU, 115 MHz (+85°С&1,8 V ±5%);

  • Two SpaceWire links(ECSS-E-50-12C, RMAP) with throughput 2–300 Mbps (–60 +85 °С); 4 channels DMA for any link; Built-in ANSI/TIA/EIA-644 LVDS transceivers with 100 Ohm impedance matching resistors;

  • Two gigabit serial links based on GigaSpaceWire (the draft standard SpaceWire-RUS) with a throughput not less than 1.25 Gbps in the range of temperatures with additional discrete frequency grid transmission 5–125 Mbps; operates on twisted pair, coax or fiber optic with the galvanic isolation external device; Link power consumption — up to 175 mW; operates on the distance up 10m to 20 m (CAT5);

  • Four MFBSP (I2S/SPI/SHARC LPORT/GPIO) links; 8 channels DMA;

  • External memory port: 32b, SRAM/ SDRAM/ NOR FLASH/NAND FLASH/ROM; Hamming code protection for all internal and external memories with a double error detection and correction of a single error;

  • Built-in the chip PLLs; Power consumption control;

  • JTAG port, built-in the chip OnCD program debugger;

  • Tools (MCStudio-4, Evaluation board); OS Linux2.6.36; RTOS uOS

  • Ceramic 240-pin Package — CQFP-240;

  • Engineering samples — from 4Q2013


RMR-02Р — Remote RMAP controller

RMR-02Р — Remote RMAP controller

  • CMOS, 0.18 mcm; Radiation Tolerant (RHBD Lib); ASIC design complexities up to 1,300,000 usable transistors;

  • Core Supply Voltage -1,8 V ±5%; I/O Supply Voltage -3,3 V ±5%;

  • Dual-port ECSS-E-50-12С SpaceWire controller with throughput 2–300 Mbps (–60 +85 °С); Built-in ANSI/TIA/EIA-644 LVDS transceivers with 100 Ohm impedance matching resistors;

  • Hardware implemented RMAP (ECSS-E-ST-50-52С) and DIP (Distributed Interrupt Protocol);

  • Build-in mini-router allows ring or star connections;

  • Two programmable universal 16-bit parallel ports with different operational modes: master, slave (mailbox), GPIO/SPI-master

  • 16-bit Intel/Motorola microcontroller interface;

  • Programmable system clock and reset outputs;

  • Maximum data rate of the parallel port 32 MB/s;

  • Maximum data rate of the SPI-master port 25 Mb/s;

  • Maximum data rate of the microcontroller interface 32 MB/s;

  • Ceramic 112-pin package CQFP-112;

  • Engineering samples — from 4Q2013


МС-24M — Dual cores DSP Microprocessor

МС-24M — Dual cores (CPU+DSP)
DSP Microprocessor

  • CMOS, 0.18 mcm; Radiation Tolerant (RHBD Lib); ASIC design complexities up to 45,000,000 usable transistors;

  • Core Supply Voltage -1,8 V ±5%; I/O Supply Voltage -3,3 V ±5%;

  • Two-cores MIMD architecture: MIPS32 compatible RISC core & FPU (32/64b) plus 2-SIMD DSP core, 120MHz (+85°С&1,8 V ±5%);

  • Two SpaceWire links(ECSS-E-50-12C, RMAP) with throughput 2–300 Mbps (–60 +85°С); 4 channels DMA for any link;

  • Four MFBSP (I2S/SPI/SHARC LPORT/GPIO) links; 8 channels DMA;

  • UART port; RT Timers;

  • External memory port: 64b, SRAM/ SDRAM/ FLASH/ ROM; Hamming code protection for all internal and external memories with a double error detection and correction of a single error;

  • Multi-channel DMA with effective support transfers and processing in DSP of the large image and signal (up to 16K words);

  • Peak performance (120 MHz): 720 MFLOPs&24е8 /960MOPs& int32/1920MOPs& int16/4320MOPs& int8;

  • Built-in the chip PLLs;

  • Power consumption control;

  • JTAG port, built-in the chip OnCD program debugger;

  • Tools (MCStudio-4, Evaluation board); OS Linux2.6.36; RTOS uOS;

  • Ceramic 416-pin Package — CPGA-416;

  • Engineering samples — from 2Q2014


МСВ-03P — the multichannel Adapter – bridge with SpW links

МСВ-03P — the multichannel Adapter –
bridge with SpW links

  • CMOS, 0.18 mcm; Radiation Tolerant (RHBD Lib); ASIC design complexities up to 47,200,000 usable transistors;

  • Core Supply Voltage -1,8 V ±5%; I/O Supply Voltage -3,3 V ±5%;

  • Architecture: the multichannel Adapter — bridge with SpW links;

  • Four SpaceWire links(ECSS-E-50-12C, RMAP) with throughput 2–300 Mbps (–60 +85 °С); Built-in ANSI/TIA/EIA-644 LVDS transceivers with 100 Ohm impedance matching resistors;

  • External memory port: SRAM/ SDRAM/ FLASH/ ROM; 32b parallel microprocessor port (including a series of Multicore microprocessors); Hamming code protection for all internal and external memories with a double error detection and correction of a single error;

  • Embedded SRAM, 8 Mbit (256KWx32b);

  • PCI (32 bit/33-66 MHz), Local Bus Specification. Rev. 2.2.;

  • Ethernet MAC with RMII 10/100 Mbps port;

  • Built-in the chip PLLs;

  • Power consumption control;

  • Engineering samples – from 4Q2013;

  • 4 SpaceWire channels;

  • Ceramic 416-pin Package — CPGA-416;

  • Engineering samples — from 4Q2013


MCK-02R — 16-channel 'Intellectual' SpaceWire  router

MCK-02R — 16-channel "Intellectual"
SpaceWire router with build-in CPU

  • CMOS, 0.25 mcm; Radiation Tolerant (RHBD Lib); ASIC design complexities up to 47,200,000 usable transistors;

  • Core Supply Voltage -2,5 V ±5%; I/O Supply Voltage -3,3 V ±5%;

  • 16-channels "intelligent" SpaceWire Router;

  • 16 SpaceWire links(ECSS-E-50-12C, RMAP) with throughput 2–250 Mbps (–60 +85°С); Built-in ANSI/TIA/EIA-644 LVDS transceivers with 100 Ohm impedance matching resistors;

  • Hardware implemented RMAP (ECSS-E-ST-50-52С) and DIP (Distributed Interrupt Protocol) for the routing parameters control;

  • Support of signal, symbol exchange, package and net stack protocols of SpaceWire;

  • Embedded MIPS32 compatible CPU core;

  • Distribution of the time and interrupt codes in accordance with SpaceWire Standard;

  • Routing management software is running under a built-in CPU-core control;

  • 32 bit parallel port for connection to signal controllers of "MULTICORE" chipset or additional external memory;

  • 25 Kbytes Embedded RAM (program and data memory for CPU core, packet memory, routing memory); Hamming code protection for all internal and external memories with a double error detection and correction of a single error;

  • UART port;

  • Tools (MCStudio-4, Evaluation board); OS Linux2.6.36; RTOS uOS;

  • Ceramic 416-pin Package — CPGA-416;

  • Engineering samples — from 2Q2014