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The SpaceWire based chipset “MultiBoard” for the space applications

IP-core

Technology

Type

Dimensions/area

Main characteristics

Notes

1

Transmitter for SpW-RT systems on twisted pair (SpFi-CML protocol)

CMOS
0,18 mcm

Soft (digital core) Hard (PLL,I/O)

470*39 5mcm/ 0,186 mm2

  • range of data rates 5 Mbps ... 1,25 Gbps (discrete series);

  • VML output levels (at the power supply voltage of the driver 1,8 -3,3 V);

  • power consumption no more than 130 mW (at the power supply voltages 1,8 V for core & PLL and 2,5 V for I/O).

The composite unit. The size and area are based on two ESD protection elements from (100 * 145 mcm), but excluding 4 adjacent pads.

2

Receiver for SpW-RT systems on twisted pair (SpFi-CML protocol)

CMOS 0,18 mcm

Soft (digital core) Hard (PLL,I/O)

470*395 mcm/ 0,186 mm2

  • range of data rates 5 Mbps ... 1,25 Gbps (discrete series);

  • VML/CML input levels (at the power supply voltage of the input analog stage 3,3 V);

  • power consumption no more than 70 mW (at the power supply voltages 1,8 V for core & PLL and 3,3 V for I/O).

The composite unit. The size and area are based on two ESD protection elements from (100 * 145 mcm), but excluding 4 adjacent pads.

3

Universal digital core & PLL of a transmitter for SpW-RT systems on twisted pair (SpFi-CML protocol)

CMOS 0,18 mcm

Soft (digital core) Hard (PLL)

470*250 mcm/0,1175 mm2

  • range of data rates 5 Mbps ... 1,25 Gbps (discrete series);

  • power consumption no more than 30 mW (at the power supply voltages 1,8 V).

TMay be used with different types of drivers (VML/CML).

4

Universal digital core & PLL of a receiver for SpW-RT systems on twisted pair (SpFi-CML protocol)

CMOS 0,18 mcm

Soft (digital core) Hard (PLL)

470*250 mcm/0,1175 mm2

  • range of data rates 5 Mbps ... 1,25 Gbps (discrete series);

  • power consumption no more than 30 mW (at the power supply voltages 1,8 V).

May be used with different types of analog input stages.

5

PLL with the frequency of the input reference signal 125 MHz and tunable frequency of the output signal 5 - 1250 MHz

CMOS 0,18 mcm

Hard

260*250mcm/0,065 mm2

The frequency of the output signal 5, 10 ... (Step 5) ... 125 MHz — the lower frequency range (LF);

312.5, 625, 1250 MHz - the upper frequency range (HF).

Supply voltage 1,8 V.

6

LVDS transmitter for the SpaceWire systems on twisted pair

CMOS 0,18 mcm

Hard

120*126 mcm/0,015 mm2

Frequency of the output signal / baud rate least 600 MHz/1200 Mbit/s.

Core supply voltage 2,5±10% V, the periphery of 3,3±10% V (± 5% is recommended).

7

LVDS receiver for the SpaceWire systems on twisted pair

CMOS 0,18 mcm

Hard

82*59 mcm/ 0,0048 mm2

Frequency of the input signal / baud rate least 600 MHz/1200 Mbit/s.

Core supply voltage 2,5±10% V, the periphery of 3,3±10% V (± 5% is recommended).

8

LVDS transmitter for the SpaceWire systems on twisted pair

CMOS 0,13 mcm

Hard

168*70 mcm/ 0,012 mm2

Frequency of the output signal/baud rate least 625 MHz/1250 Mbit/s.

Core supply voltage VDD = 1,2±10% V, the periphery VD33 = 3,3±10% V (± 5% is recommended).

Power consumption of VDD at a frequency of 300/625 MHz (square wave) is not more than 0,15 /0,3 mW.

Power consumption from VD33 at 300/625 MHz (square wave) is not more than 29/33 mW.

9

LVDS receiver for the SpaceWire systems on twisted pair

CMOS 0,13 mcm

Hard

86*49 mcm/ 0,042 mm2

Frequency of the input signal/baud rate least 625 MHz/1250 Mbit/s.

Core supply voltage VDD=1,2±10% V, the periphery VD33 = 3,3±10% V (±5 % is recommended).

Power consumption of VDD at a frequency of 300/625 MHz (square wave) is not more than 0,47/0,62 mW.

Power consumption from VD33 at 300/625 MHz (square wave) is not more than 0,45 mW (slow dependent on the frequency).

10–13

PLL for the system clock synchronization of the high-speed processor units for the frequency range of 1–400 MHz

CMOS 0,25/0,18 mcm

Hard

-/0,35-0,42 mm2

Frequency of the output signal is equal to the product of the coefficient K (K = ½, 1, 2, 3

... 199, 200) and the frequency of the reference signal of 2 MHz.

Jitter in the range of reference frequencies 10 ... 30 MHz:

550 ... 180 ps — VCO by inverting elements;

600 ... 200 ps — VCO by differential stages.

Current consumption in the range of reference frequencies 10 ... 30 MHz:

1,6 ... 4,3 mA — VCO by inverting elements;

2,9 ... 8,0 mA — VCO by differential stages.

Supply voltage 2,3 ... 3,3 V.

Has two embodiments differing types of the voltage controlled oscillator (VCO): VCO by inverting elements and VCO by differential stages.

14–15

PLL for the system clock synchronization of the high-speed processor units for the frequency range of 1–930 MHz

CMOS 0,25/0,18 mcm

Hard

-/0,35-0,42 mm2

Frequency of the output signal is 1 ... 31 * (10–30) MHz.

Jitter at the reference frequency of 2 MHz up to 1 ns.

Current consumption at the reference frequency of 2 MHz up to 2,7 mA. S

upply voltage 2,3 ... 3,3 V.